The present invention relates generally to an apparatus and method for grinding a semiconductor wafer surface and, in particular, to grinding techniques that can be used to planarize a semiconductor surface during the fabrication of an integrated circuit.
In the process of fabricating modern semiconductor integrated circuits (ICs), it is necessary to form various material layers and structures over previously-formed layers and structures. However, the prior formations often leave the top surface topography of an in-process wafer highly irregular, with bumps, areas of unequal elevation, troughs, trenches and/or other surface irregularities. Such irregularities cause problems when forming the next layer. For example, when printing a photolithographic pattern having small geometries over previously-formed layers, a very shallow depth of focus is required. Accordingly, it becomes essential to have a flat and planar surface. Otherwise, some parts of the pattern will be in focus and others will not. Surface variations on the order of less than 1,000 angstroms (.ANG.) over a 25.times.25 millimeter (mm) exposure area are preferred. Additionally, if the irregularities are not leveled at each major processing step, the surface topography of the wafer can become even more irregular, causing further problems as the layers stack up during further processing. Depending on the die type and the size of the geometries involved, the surface irregularities can lead to poor yield and device performance. Consequently, it is desirable to planarize, or level, the IC structures.
One technique for planarizing the surface of a wafer is chemical mechanical polishing (CMP). In general, CMP planarization involves holding a thin flat semiconductor wafer against a rotating wetted polishing surface, such as a compliant polishing pad, under a controlled downward pressure. During the CMP process, a slurry is provided to remove and flush away unwanted film material. In one exemplary implementation, a CMP process is used to remove an oxide coating to the level of previously-formed IC structures. In such processes, it is important to remove a sufficient amount of material to provide a smooth surface without removing an excessive amount of underlying materials.
Although CMP processes have proved useful in the fabrication of semiconductor ICs, they suffer from several drawbacks. First, CMP processes are relatively slow, with a removal rate on the order of about 1 micron per minute (.mu./min), and, therefore, limit the overall throughput of the fabrication process. Second, polishing pads typically used in CMP processes tend to have relatively short lifetimes and must be replaced frequently. Third, the use of slurry and other chemicals during the CMP process increases the overall cost of fabrication and results in the need for additional waste removal.
Grinding processes, in which a grinding wheel is pressed against the wafer surface to grind away semiconductor material, are sometimes used by manufacturers of semiconductor wafers to planarize the wafer surface or provide a smooth wafer edge. Grinding processes can avoid some of the foregoing problems associated with CMP processes. However, as explained below, such grinding processes have not generally been used during the fabrication of semiconductor ICs.
The topography of the front surface of a wafer may vary by as much as 1-2 microns (.mu.) as a result of the natural distortions or warpage of the wafer as well as variations in the thickness of the wafer across its surface. In contrast to CMP processes in which the wafer is supported by a compliant pad, grinding processes use a hard grinding surface to remove from the wafer surface all materials in substantially an absolute geometrical reference plane. Therefore, because of the wafer's front surface topography, it is difficult to use a grinding process to planarize a wafer having one or more previously-formed layers without removing an excessive amount of underlying materials on at least some parts of the wafer.
Despite the apparent difficulties in using grinding processes to planarize the wafer during the fabrication of ICs, it would be beneficial to provide a planarization technique based on a grinding process that can provide a substantially flat surface across the entire wafer and that can overcome some of the drawbacks associated with current CMP processes.